（AD17 PCB短路约束报错）有遇到这个问题的吗，怎么解决

报错位置在一个芯片的各个引脚上，报错内容为：
essing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Violation between Short-Circuit Constraint: Between Pad FDMC1-5(40.31mm,55.921mm) on Top Layer And Pad FDMC1-9(39.13mm,56.896mm) on Top Layer Location : [X = 0mm][Y = 0mm]