【Verilog】4x4矩形薄膜键盘,利用状态机进行扫描

写了一个状态机,按照列进行依次扫描,最后状态机发现只有一列(即设置的初始状态列)有正常输出,其余三列没有输出。状态机对4列状态是无条件转移,即在1k的时钟上升沿依次序跳转的下一列扫描状态。利用tb文件扫描正常,但是实物始终只有一列的输出。(ps:col为output,row为input)谢谢各位!

            //两段式状态机
    
    always@(posedge clk_1kHz ) begin
            if(!rst_n)   state <= 3'd1;              //状态机进入的初始状态,从第一列开扫
            else  state <= nextstate;
    end
    
    //通过组合逻辑判断按键输出
    always@(state or row) begin
            case (state)
                1:begin
                        col = 4'b0001;
                        case(row)
                            4'b0001: begin code = 4'b0000; valid = 1; SEG = 8'b1111_1100; end
                            4'b0010: begin code = 4'b0100; valid = 1; SEG = 8'b0110_0110; end
                            4'b0100: begin code = 4'b1000; valid = 1; SEG = 8'b1111_1110; end
                            4'b1000: begin code = 4'b1100; valid = 1; SEG = 8'b1001_1100; end
                            default: begin code = 4'b1111; valid = 0; SEG = 8'b0000_0000; end
                        endcase
                        if(valid) nextstate = 3'd1;                  //如果是有效输入继续停留在该状态,否则扫描下一列
                        else nextstate = 3'd2;
                  end
                 2:begin
                        col = 4'b0010;
                        case(row)
                            4'b0001: begin code = 4'b0001; valid = 1; SEG = 8'b0110_0000; end
                            4'b0010: begin code = 4'b0101; valid = 1; SEG = 8'b1011_0110; end
                            4'b0100: begin code = 4'b1001; valid = 1; SEG = 8'b1111_0110; end
                            4'b1000: begin code = 4'b1101; valid = 1; SEG = 8'b0111_1010; end
                            default: begin code = 4'b1111; valid = 0; SEG = 8'b0000_0000; end
                        endcase
                        if(valid) nextstate = 3'd2;
                        else nextstate = 3'd3;
                        
                  end
                  3:begin
                        col = 4'b0100;
                        case(row)
                            4'b0001: begin code = 4'b0010; valid = 1; SEG = 8'b1101_1010; end
                            4'b0010: begin code = 4'b0110; valid = 1; SEG = 8'b1011_1110; end
                            4'b0100: begin code = 4'b1010; valid = 1; SEG = 8'b1110_1110; end
                            4'b1000: begin code = 4'b1110; valid = 1; SEG = 8'b1001_1110; end
                            default: begin code = 4'b1111; valid = 0; SEG = 8'b0000_0000; end
                        endcase
                        
                        if(valid) nextstate = 3'd3;
                        else nextstate = 3'd4;
                  end
                  4:begin
                        col = 4'b1000;
                        case(row)
                            4'b0001: begin code = 4'b0011; valid = 1; SEG = 8'b1111_0010; end
                            4'b0010: begin code = 4'b0111; valid = 1; SEG = 8'b1110_0000; end
                            4'b0100: begin code = 4'b1011; valid = 1; SEG = 8'b0011_1110; end
                            4'b1000: begin code = 4'b1111; valid = 1; SEG = 8'b1000_1110; end
                            default: begin code = 4'b1111; valid = 0; SEG = 8'b0000_0000; end
                        endcase
                        
                        if(valid) nextstate = 3'd4;
                        else nextstate = 3'd1;
                  end
                  default: begin col = 4'b0100; valid = 0; code = 4'b1111 ; nextstate = 3'd3; SEG = 8'b0000_0000; end  //无效状态数码管不显示
                endcase
    end