用Verilog的异步计数器报错10200

想编写一个异步计数器74LS90，但quartus 报了这样的错误：
Error (10200): Verilog HDL Conditional Statement error at _7490.v(16): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
请问有人知道是为什么吗，下面是源代码：

module _7490(CPa,S91,S92,R01,R02,Qd,Qc,Qb,Qa);

input CPa;
input S91,S92;
input R01,R02;
output Qd,Qc,Qb,Qa;
reg[2:0] Q;
reg Qa;
parameter Model = 5;

always@(    negedge CPa or 
            posedge R01 or 
            posedge R02 or 
            posedge S91 or 
            posedge S92 )begin
        if(S91&&S92)
        Qa <= 1'b1;
    else begin
        if(R01&&R02)
            Qa <= 1'b0;
        else
            Qa <= ~Qa;
    end
end

always@(    negedge Qa or 
            posedge R01 or 
            posedge R02 or 
            posedge S91 or 
            posedge S92 )begin
    if(S91&&S92)
        Q <= 3'b100;
    else begin
        if(R01&&R02)
            Q <= 3'b000;
        else begin
            if(Q == Model-1)
                Q <= 3'b000;
            else
                Q <= Q+1'b1;
        end
    end
end

assign {Qd,Qc,Qb} = Q;

endmodule