```
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
_always @(posedge clk)
if(resetn==0)
q<=16'b0;
else if(byteena==2'b00)
q<=d;
else if(byteena==2'b01)
q[7:0]<=d[7:0];
else if(byteena==2'b10)
q[15:8]<=d[15:8];
else
q<=d;
endmodule
```__
找到错误了，byteena==2'b00) q<=d;q应该等于q