questasim编译vhdl,第一行提示错误,请问是哪里不对?

Error: (vlog-13069) fulladd.vhd(2): near ";": syntax err
or, unexpected ';', expecting STRING_LITERAL or a tick-double-quoted string literal.

代码:

library ieee ;
use ieee.std_logic_1164.all;
entity fau is
  port(a,b,cin:in std_logic;
       s,cout:out std_logic);
end fau;
architecture Behavioral of fau is
begin
  s<=( a xor b xor cin);
  cout<=(a and b) or (a and cin) or (b and cin);
end process
end behavioral;

同问,被这个问题坑死了