always @(posedge clk or negedge rst or negedge outkey)
if(!rst) count1<=0;
else if(count1<30000000000) count1<=count1+1;
else count1<=0;
assign timert=count1[34];
endmodule
Error (10200): Verilog HDL Conditional Statement error at top.v(41): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
count1计数器，位宽多少，是不是一直处在计数死循环，就是count1始终＜你的elseif里面的数值