module seq_detector(clk, reset, d, y);
input clk, reset, d;
output y;
reg [2 : 0] state;
wire y;
parameter s0 = 4'b0000, s1 = 4'b0001, s2 = 4'b0010, s3 = 4'b0100,
s4 = 4'b1000, s5 = 4'b1001, s6 = 4'b1010, s7 = 4'b1011,s8=1100;
always@(posedge clk or posedge reset)
begin
if(reset) state <= s0;
else
begin
casex(state)
s0: begin
if(d == 0) state <= s1;
else state <= s0;
end
s1: begin
if(d == 1) state <= s2;
else state <= s1;
end
s2: begin
if(d == 0) state <= s3;
else state <= s0;
end
s3: begin
if(d == 1) state <= s4;
else state <= s1;
end
s4: begin
if(d == 1) state <= s5;
else state <= s3;
end
s5: begin
if(d == 0) state <= s6;
else state <= s0;
end
s6: begin
if(d == 1) state <= s7;
else state <= s1;
end
s7: begin
if(d == 0) state <= s8;
else state <= s0;
end
s8:begin
if(d == 1) state <= s0;
else state <= s1;
end
default: state <= s0;
endcase
end
end
endmodule
不知道对不对，求大佬指导下