Verilog实例化传参报错[Synth 8-2900]

Verilog传参非法输入是为什么鸭

报错信息：

[Synth 8-2900] ignoring illegal expression in output port connection 
[Synth 8-685] variable 'bit' should not be used in output port connection 
 

代码：

module scan_led_disp(
    input clk,reset,
    input rst,
    output [6:0]out,
    output reg [3:0]bit
     );
    localparam N=28;            //对输入的时钟分频
    reg[N-1:0] regN;
    reg[3:0]num;
    always @(posedge clk, posedge rst)
    begin
    if(rst) 
        regN<=0;
    else
        regN<=regN+1;
    end
    always@*
    begin
    case(regN[N-1:N-2])
      2'b00: 
        begin
        bit[0]=1;
        num=4'b0001;
        end
      2'b01:
        begin
        bit[1]=1;
        num=4'b0010;
        end
      2'b10:
        begin
        bit[2]=0;
        num=4'b0100;
        end
      2'b11:
        begin
        bit[3]=0;
        num=4'b1000;
        end
      endcase
      end
 sevendecoder
  show1(num , 1'b1 ,1'b1,1'b1 , out , 1'b1 , bit[0]);
 sevendecoder
  show2(num , 1'b1 ,1'b1,1'b1 , out , 1'b1, bit[1]);
 sevendecoder
  show3(num , 1'b1 ,1'b1,1'b1 , out , 1'b1, bit[2]);
 sevendecoder
  show4(num , 1'b1 ,1'b1,1'b1 , out , 1'b1, bit[3]);
 endmodule

//数码管显示
module sevendecoder(
input[3:0]in,
input IB,
input LT,
input RBI,
output reg[6:0] out,
output reg RBO,
output  bit
);
always@*
begin
out = 7'b0000000;
RBO = 1'b0;
if(IB==1'b0)
begin
out = 7'b0000000;
end
else if(LT==1'b0)
begin
 out = 7'b1111111;
RBO = 1'b1;
end
else if(RBI==1'b0)
begin
if(in==4'b0000) begin
out = 7'b0000000;
RBO=1'B0; end
end
else
case (in)
4'b0000 : out = 7'b1111110;
4'b0001 : out = 7'b0110000;
4'b0010 : out = 7'b1101101;
4'b0011 : out = 7'b1111001;
4'b0100 : out = 7'b0110011;
4'b0101 : out = 7'b1011011;
4'b0110 : out = 7'b1011111;
4'b0111 : out = 7'b1110000;
4'b1000 : out = 7'b1111111;
4'b1001 : out = 7'b1111011;
4'b1010 : out = 7'b0001101;
4'b1011 : out = 7'b0011001;
4'b1100 : out = 7'b0100011;
4'b1101 : out = 7'b1001011;
4'b1110 : out = 7'b0001111;
4'b1111 : out = 7'b0000000;
endcase
end
endmodule

 

这个里面好像好你这问题一样。