moudle gates( input wire a, input wire b, outpu

moudle gates( input wire a, input wire b, output wire[5:0] z ); assign z[5]= a&b; assign z[4]= ~(a&b); assign z[3]= a|b; assign z[2]= ~(a|b); assign z[1]= a^b； assign z[0]= a~^b; endmoudle 请问为什么报错呢 quartus软件