module divx(clkin,rst,bin,ledout
);
input clkin,rst;
input [3:0]bin;
output reg [1:0] ledout;
reg clkout;
reg [31:0] cnt_1s;
reg [3:0] cnt;
reg [3:0] tp;
always @ (posedge clkin or posedge rst)
if(rst==1)//由于按键是按下为高电平,不按下时为低电平,所以当按下时触发清零信号
cnt_1s<=0;
else if(cnt_1s==99999999)
cnt_1s<=0;
else
cnt_1s<=cnt_1s+1;
always @ (posedge clkin or posedge rst)
if(rst==1)
begin
clkout<=0;
ledout[0]<=0;
end
else if(cnt_1s<=49999999)
begin
clkout<=0;
ledout[0]<=0;
end
else
begin
clkout<=1;
ledout[0]<=1;
end
always @ (posedge clkin or posedge rst)
if(rst==1)
ledout[1]<=0;
else if(bin>1)
begin
if(cnt==8)
ledout[1]<=1;
else
ledout[1]<=0;
end
else if(bin==1)
ledout[1]<=clkout;
else if(bin==0)
ledout[1]<=1;
always @ (posedge clkout or posedge rst)
if(rst==1)
cnt<=(8-tp+1);
else if(cnt==8)
cnt<=(8-tp+1);
else
cnt<=cnt+1;
always @(posedge clkin or posedge rst)
begin
case(bin)
4'b0001: tp<=4'b0001;
4'b0010: tp<=4'b0010;
4'b0011: tp<=4'b0011;
4'b0100: tp<=4'b0100;
4'b0101: tp<=4'b0101;
4'b0110: tp<=4'b0110;
4'b0111: tp<=4'b0111;
4'b1000: tp<=4'b1000;
default: tp<=4'b1000;
endcase
end
endmodule