老师布置的任务,要求用加法器和D触发器构成延时链实现TDC电路,不能用Verilog语言直接编写,要用FPGAeditor手动布线,求FPGAeditor的详细教程,谢谢了!
https://download.csdn.net/download/u010651546/9682065https://download.csdn.net/download/fcc2008/10764298