QUQRTUS ii 编译时出现10170错误，但是自己没发现哪里错了，求大神指正

代码：
module time_min(IClk,OM,OS);//IClk:IClk:clock signal,OM:output mintute,OS:output second
input IClk;
output[5:0] OM,OS;
reg[5:0] OM,OS;
reg MSig;
always@(posedge IClk)
begin
time_sec T1(IClk,OS,MSig);
if(MSig==1'b1)
begin
if(OM==6'd59)
OM<=0;
else OM<=OM+1;
end
end
endmodule
time_sec代码：
module time_sec(IClk,OS,OSig);//IClk:clock signal,OS:output second,OSig:the signal of carry bit
input IClk;
output[5:0] OS;
output OSig;
reg[5:0] OS;
reg OSig;
always@(posedge IClk)
begin
if(OS==6'd59)//one minitute is 60 second
begin
OS<=0;
OSig<=1;
end
else
begin
OS<=OS+1;
OSig<=0;
end;
end
endmodule

求大佬给解决一下啊，初学者简直要哭了

语言是VHDL, 而错误提示中出现Verilog. 显然属于基本设置错误, cut/paste党的通病.
可能1: jishu01扩展名错误,应当为.vhd
可能2: project里面new file时选择了verilog, 应选VHDL
可能3: Setting里可能有VHDL / Verilog选设按钮错选了verilog. 但一般IDE允许混编,最多Warning.