下面这个verilog的分频求讲解以下具体意思？谢谢！

reg CLK_DIV;
reg [31:0]DCLK_DIV;

parameter CLK_FREQ = 'D50_000_000;
parameter DCLK_FREQ = 'D10;

always @(posedge clk)
if(DCLK_DIV < (CLK_FREQ / DCLK_FREQ))
DCLK_DIV <= DCLK_DIV+1'b1;

else
begin
DCLK_DIV <= 0;
CLK_DIV <= ~CLK_DIV;

end