verilog顶层文件出现了问题
module Count (rst_n,clk,outh);
input rst_n,clk;
output [3:0] outh;
reg [2:0] out2;
reg [3:0] pout;
always@(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
out2 <= 0;
end
else
begin
out2 <= out2+1;
end
end
always@(posedge clk)
begin
case(out2)
4'b000:pout<=4'd0;
4'b001:pout<=4'd1;
4'b010:pout<=4'd2;
4'b011:pout<=4'd3;
4'b100:pout<=4'd4;
4'b101:pout<=4'd5;
4'b110:pout<=4'd6;
4'b111:pout<=4'd7;
default:pout<=4'd0;
endcase
end
assign outh=pout;
endmodule
这个是计数器模块单独仿真没问题
我把它放到顶层里 
输入输出没边 仿真就出现问题了
求解释（DetecDdge模块单独仿真和放到顶层仿真都没问题）