modelsim仿真Verilog，调用monitor，没有显示是什么问题？

1.写一个Verilog八位2选一，使用modelsim平台，调用monitor查看仿真结果
但是什么都不显示，编译也没有问题
2.选择器文件如下：

module mux (out, sel, b, a);

parameter size = 8;

output [size-1:0] out;
input [size-1:0] b, a;
input sel;

assign out = (!sel) ? a :                   
        (sel)  ? b :                  
        {size{1'bx}} ; 

endmodule

3.测试文件如下：

    reg  [`width:1] b,a;     
wire [`width:1] out;     
reg sel; 

// Instantiate the mux. Named mapping allows the designer to have freedom // with the order of port declarations. #8 overrides the parameter (NOT // A DELAY), and gives the designer flexibility naming the parameter.

mux #(`width) m1 (.out(out), .sel(sel), .b(b), .a(a));  

initial       
begin  

// Display results to the screen, and store them in an SHM database

$monitor($time,,"sel=%b a=%b b=%b out=%b", sel, a, b, out);

$dumpvars(2,mux_test);

// Provide stimulus for the design

sel=0; b={width{1'b0}}; a={width{1'b1}};

#5 sel=0; b={width{1'b1}}; a={width{1'b0}};

#5 sel=1; b={width{1'b0}}; a={width{1'b1}};

#5 sel=1; b={width{1'b1}}; a={width{1'b0}};

#5 $finish; 

   end

endmodule

感谢知道的告诉一下，xie'x